Field of the Invention
The present invention relates to a semiconductor device and particularly relates to the structure of penetration electrodes provided in a semiconductor device.
Description of Related Art
Storage capacity required for semiconductor devices such as DRAM (Dynamic Random Access Memory) has been increasing year after year. In recent years, a method has been proposed to satisfy such requirements in which a plurality of semiconductor chips is stacked and connected electrically via penetration electrodes (i.e. TSV: Through Silicon Via) arranged in a silicon substrate (see Japanese Patent Application Laid-open No. 2011-86773 and No. 2010-153492).
The penetration electrodes are electrically connected to wiring pads provided in a multi-level wiring structure formed on the main surface of the semiconductor substrate. Each of the penetration electrodes is electrically connected to a corresponding circuit block(s) via a wiring pad. There are two kinds of the penetration electrodes. One is a signal penetration electrode for transmitting signal such as a command signal and an address signal. And the other is a power penetration electrode for supplying a power voltage. A wiring pad provided for a power penetration electrode requires a larger area than a wiring pad provided for a signal penetration electrode in order to supply a power voltage stably to a plurality of stacked semiconductor chips.
A plurality of penetration electrodes including signal penetration electrodes and power penetration electrodes are aligned two-dimensionally on a semiconductor chip. In the multi-level wiring structure where the penetration electrodes are arranged, a wiring pad is provided for each of the plurality of penetration electrodes and various kinds of wirings such as a signal line and a power line are arranged in a space between the plural wiring pads. Here, as stated above, a wiring pad of the power penetration electrode has a larger area than a wiring pad of the signal penetration electrode. Accordingly, in the multi-level wiring structure where these plural penetration electrodes are arranged, the number of wirings to be arranged between the pad electrodes is limited because of its larger area.